1. Field of the Invention
The invention relates to a semiconductor device with a plurality of terminals and to a method of manufacturing the device.
2. Description of the Background Art
In association with recent miniaturization of a package, a semiconductor of ball grid array (BGA) type or land grid (LGA) type, in which external electrodes are arranged in a matrix pattern on the entire back surface of a substrate, has become pervasive.
A conventional semiconductor device and a method of manufacturing the device will be described hereinbelow by reference to FIGS. 9 through 17.
FIG. 9 is a view showing a front surface of a conventional semiconductor device; FIG. 10 is a cross-sectional view of the semiconductor device shown in FIG. 9; FIG. 11 is a view showing the back surface of the semiconductor device shown in FIG. 9; FIG. 12 is a perspective view showing an interior of a resin-sealed section shown in FIG. 9; FIG. 13 is a cross-sectional view of the resin-sealed section taken along line b-b shown in FIG. 12; FIG. 14 is a view showing areas of the resin-sealed section to be sliced; FIG. 15 is an enlarged view of areas on the back side of the semiconductor device to be sliced; FIG. 16 is a cross-sectional view of sliced semiconductor devices; and FIG. 17 is a cross-sectional view of a neighborhood of a solder ball shown in FIG. 16.
In FIGS. 9 through 17, reference numeral 1 designates a substrate for manufacturing semiconductor devices; 2 designates a resin-sealed section; 3 designates solder balls; 4 designates a semiconductor chip; 5 designates a wire; 6 designates an area to be sliced; 8 designates a package; and 9 designates a land.
First, a conventional semiconductor device will be described.
As shown in FIGS. 9 and 10, a plurality of resin-sealed sections 2 are formed on the surface of a substrate 1. As shown in FIG. 11, a plurality of solder balls 3 are formed on the back surface of the substrate 1 so as to correspond to the respective resin-sealed sections 2. Specifically, as shown in FIG. 17, the solder balls 3 are formed on the back surface of the substrate 1 via corresponding lands 9.
As shown in FIGS. 12 and 13, a plurality of semiconductor chips 4 electrically connected to the substrate 1 by means of wires 5 are provided in the resin-sealed sections 2.
As shown in FIGS. 14 through 16, an area to be sliced (hereinafter called a “slice area”) 6 is provided in each of the resin-sealed sections 2 located in a position between the adjacent semiconductor chips 4 (or packages 8).
As shown in FIGS. 15 and 16, the plurality of solder balls 3, which serve as terminals for external electrodes, are provided on each of the semiconductor chips 4 (or the packages 8) at uniform pitches B of, e.g., 0.8 mm. An interval C between the corresponding solder balls 3 of the adjacent packages 8 (i.e., a package-to-package pitch) is a sum of a desired package size and the width of the slice area 6. For instance, in a case where a package size is 8 mm×8 mm and the width of the slice area 6 is 0.35 mm, the package-to-package pitch C is 8.35 mm.
Next, there will now be described a method of manufacturing the above-mentioned semiconductor device.
First, the plurality of semiconductor chips 4 are mounted on the surface of the substrate 1. The substrate 1 and the semiconductor chips 4 are electrically connected by use of the wires 5.
Next, the plurality of semiconductor chips 4 are collectively sealed with resin, thus forming the resin-sealed sections 2.
Further, the lands 9 to be used for mounting solder balls are formed on the back surface of the substrate 1. The solder balls 3 are formed on the lands 9. Here, in the case of a semiconductor device of LGA, formation of the solder balls 3 is obviated.
The resin-sealed sections 2, which have been collectively molded, are sliced along the cut areas 6 by means of a dicing saw, whereby the resin-sealed sections 2 are divided into a plurality of packages (semiconductor devices) 8.
Each of the packages 8 is subjected to an electrical test.
As mentioned above, when each of the packages 8 is subjected to an electrical test, a test tool such as a test contact pin must be prepared every time a package size is different. Therefore, cost of the test tool is too high.
Further, no electrical test can be carried out during a period in which a test tool is replaced with another test tool, thereby resulting in inefficient conduction of an electrical test; that is, occurrence of so-called package switching loss.
When a package is miniaturized to an extent to be called a chip-scale package (CSP), a resultant package becomes too small or lightweight. Such packages will fall during the course of a test or transport.
A method effective for solving the problem is to simultaneously subject the plurality of semiconductor chips 4 to a test while the semiconductor chips 4 (or packages 8) are sliced into pieces or collectively sealed with resin on the substrate 1.
However, a package size has already been determined by a standardization institution, such as a Japanese Electronics and Information Technology Industries Associations). The interval C between the corresponding solder balls 3 of the adjacent packages 8 (i.e., the package-to-package pitch C) is not necessarily an integral multiple of the interval B between the solder balls 3 in the package 8 (i.e., a ball pitch). Therefore, even in the case of a package of same size, a test tool must be prepared every time the intervals B and C are changed. Thus, costs for the tool cannot be curtailed.
Moreover, when packages of different sizes are manufactured, test tools for the respective packages must be prepared, thereby hindering curtailment of costs for the tools.
Accordingly, since commonality cannot be achieved in connection with positions of terminals (e.g., solder balls) 3 on the back side of the substrate 1, a test tool must be prepared every time the interval C between the solder balls C of the adjacent packages 8 or a package size has become changed. For this reason, costs for the test tool cannot be diminished.
A necessity for replacement of test tools entails occurrence of so-called package switching loss.